View MC14538B_4850302.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2005 february, 2005 ? rev. 6 1 publication order number: MC14538B/d MC14538B dual precision retriggerable/resettable monostable multivibrator the MC14538B is a dual, retriggerable, resettable monostable multivibrator. it may be triggered from either edge of an input pulse, and produces an accurate output pulse over a wide range of widths, the duration and accuracy of which are determined by the external timing components, c x and r x . output pulse width t = r x c x (secs) r x = c x = farads features ? unlimited rise and fall time allowed on the a trigger input ? pulse width range = 10 s to 10 s ? latched trigger inputs ? separate latched reset inputs ? 3.0 vdc to 18 vdc operational limits ? triggerable from positive (a input) or negative?going edge (b?input) ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pin?for?pin compatible with mc14528b and cd4528b (cd4098) ? use the mc54/74hc4538a for pulse widths less than 10 s with supplies up to 6 v ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a operating temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com marking diagrams pdip?16 p suffix case 648 MC14538Bcp awlyyww soic?16 dw suffix case 751g a = assembly location wl, l = wafer lot yy, y = year ww, w = work week soeiaj?16 f suffix case 966 MC14538B awlyww see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 16 1 1 16 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techni q ues reference manual, solderrm/d. 14538b awlyyww 16 1 soic?16 d suffix case 751b tssop?16 dt suffix case 948f 14538b awlyww 14 538b alyw 1 16 1 16
MC14538B http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 a b reset b c x /r x b v ss v dd q b q b b b a a reset a c x /r x a v ss v ss q a q a b a block diagram v dd v dd 6 7 10 9 12 11 5 4 a b c x r x 12 q1 q1 reset 3 c x r x 15 14 q2 q2 reset 13 a b r x and c x are external components. v dd = pin 16 v ss = pin 8, pin 1, pin 15 one?shot selection guide 100 ns mc14528b mc14536b MC14538B mc14541b mc4538a* 1 s 10 s 100 s 1 ms 10 ms 100 ms 1 s 10 s *limited operating voltage (2 - 6 v) total output pulse width range recommended pulse width range 23 hr 5 min. ordering information device package shipping 2 MC14538Bcp pdip?16 500 units / rail MC14538Bcpg pdip?16 (pb?free) 500 units / rail MC14538Bd soic?16 48 units / rail MC14538Bdg soic?16 (pb?free) 48 units / rail MC14538Bdr2 soic?16 2500 units / tape & reel MC14538Bdr2g soic?16 (pb?free) 2500 units / tape & reel MC14538Bdw soic?16 wb 47 units / rail MC14538Bdwr2 soic?16 wb 1000 units / tape & reel MC14538Bdwr2g soic?16 wb (pb?free) 1000 units / tape & reel MC14538Bdtr2 tssop?16* 2500 units / tape & reel MC14538Bf soeiaj?16 50 units / rail MC14538Bfg soeiaj?16 (pb?free) 50 units / rail MC14538Bfel soeiaj?16 2000 units / tape & reel MC14538Bfelg soeiaj?16 (pb?free) 2000 units / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
MC14538B http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd ? 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (note 2) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 ? ? ? ? 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 ? ? ? ? 1.7 0.36 0.9 2.4 ? ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current, pin 2 or 14 i in 15 ? 0.05 ? 0.00001 0.05 ? 0.5 adc input current, other inputs i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance, pin 2 or 14 c in ? ? ? ? 25 ? ? ? pf input capacitance, other inputs (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) q = low, q = high i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc quiescent current, active state (both) (per package) q = high, q = low i dd 5.0 10 15 ? ? ? 2.0 2.0 2.0 ? ? ? 0.04 0.08 0.13 0.20 0.45 0.70 ? ? ? 2.0 2.0 2.0 madc total supply current at an external load capacitance (c l ) and at external timing network (r x , c x ) (note 3) i t 5.0 10 i t = (3.5 x 10 2 ) r x c x f + 4c x f + 1 x 10 5 c l f i t = (8.0 x 10 2 ) r x c x f + 9c x f + 2 x 10 5 c l f i t = (1.25 x 10 1 ) r x c x f + 12c x f + 3 x 10 5 c l f where: i t in a (one monostable switching only), where: c x in f, c l in pf, r x in k ohms, and where: f in hz is the input frequency. adc 2. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 3. the formulas given are for the typical characteristics only at 25 c.
MC14538B http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (note 4) (c l = 50 pf, t a = 25 c) v all types characteristic symbol v dd vdc min typ (note 5) max unit output rise time t tlh = (1.35 ns/pf) c l + 33 ns t tlh = (0.60 ns/pf) c l + 20 ns t tlh = (0.40 ns/pf) c l + 20 ns t tlh 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns output fall time t thl = (1.35 ns/pf) c l + 33 ns t thl = (0.60 ns/pf) c l + 20 ns t thl = (0.40 ns/pf) c l + 20 ns t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time a or b to q or q t plh , t phl = (0.90 ns/pf) c l + 255 ns t plh , t phl = (0.36 ns/pf) c l + 132 ns t plh , t phl = (0.26 ns/pf) c l + 87 ns t plh , t phl 5.0 10 15 ? ? ? 300 150 100 600 300 220 ns reset to q or q t plh , t phl = (0.90 ns/pf) c l + 205 ns t plh , t phl = (0.36 ns/pf) c l + 107 ns t plh , t phl = (0.26 ns/pf) c l + 82 ns 5.0 10 15 ? ? ? 250 125 95 500 250 190 ns input rise and fall times reset t r , t f 5 10 15 ? ? ? ? ? ? 15 5 4 s b input 5 10 15 ? ? ? 300 1.2 0.4 1.0 0.1 0.05 ms a input 5 10 15 no limit ? input pulse width a, b, or reset t wh , t wl 5.0 10 15 170 90 80 85 45 40 ? ? ? ns retrigger time t rr 5.0 10 15 0 0 0 ? ? ? ? ? ? ns output pulse width e q or q refer to figures 8 and 9 c x = 0.002 f, r x = 100 k t 5.0 10 15 198 200 202 210 212 214 230 232 234 s c x = 0.1 f, r x = 100 k 5.0 10 15 9.3 9.4 9.5 9.86 10 10.14 10.5 10.6 10.7 ms c x = 10 f, r x = 100 k 5.0 10 15 0.91 0.92 0.93 0.965 0.98 0.99 1.03 1.04 1.06 s pulse width match between circuits in the same package. c x = 0.1 f, r x = 100 k 100 [(t 1 t 2 )/t 1 ] 5.0 10 15 ? ? ? 1.0 1.0 1.0 5.0 5.0 5.0 % 4. the formulas given are for the typical characteristics only at 25 c. 5. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. ????????????????????????????????? ????????????????????????????????? operating conditions external timing resistance r x ? 5.0 ? (note 6) k external timing capacitance c x ? 0 ? no limit (note 7) f 6. the maximum usable resistance r x is a function of the leakage of the capacitor c x , leakage of the MC14538B, and leakage due to board layout and surface resistance. susceptibility to externally induced noise signals may occur for r x > 1 m .. 7. if c x > 15 f, use discharge protection diode per fig. 11.
MC14538B http://onsemi.com 5 figure 1. logic diagram (1/2 of device shown) note: pins 1, 8 and 15 must be externally grounded - + - + v dd v dd p1 r x c x 2 1 (14) (15) 4 (12) 5(11) 3 (13) a b reset v ss n1 v ref1 c1 c2 enable v ref2 enable control s reset latch q r q r r s r s q q 6(10) 7(9) output latch figure 2. power dissipation test circuit and waveforms 500 pf v dd 0.1 f ceramic r x r x c x v ss c x v ss v in c x /r x a b reset a b reset q q q q v ss c l c l c l c l 20 ns 20 ns v dd 0 v 90% 10% v in i d input connections characteristics reset a b t plh , t phl , t tlh , t thl , t, t wh , t wl v dd pg1 v dd t plh , t phl , t tlh , t thl , t, t wh , t wl v dd v ss pg2 t plh(r) , t phl(r) , t wh , t wl pg3 pg1 pg2 figure 3. switching test circuit *includes capacitance of probes, wiring, and fixture parasitic. note: switching test waveforms for pg1, pg2, pg3 are shown in figure 4. v dd r x r x v ss c x c x /r x a b reset a b reset q q q q c l c x c l c l c l v ss pulse generator pulse generator pulse generator v ss *c l = 50 pf pg1 = pg2 = pg3 =
MC14538B http://onsemi.com 6 figure 4. switching test waveforms reset a b t plh q q 50% t wh 90% 10% t tlh t thl t wl t thl t phl t thl 90% 10% 50% t 50% 50% 50% 90% 10% t plh t thl t tlh t phl t wl 50% 90% 10% t phl t phl t tlh t thl t plh 50% 50% 90% 10% 50% 50% 50% t rr 50% v dd v dd v dd t tlh figure 5. typical normalized distribution of units for output pulse width figure 6. typical pulse width variation as a function of supply voltage v dd 0 0.2 0.4 0.6 0.8 1.0 -4 -2 0 2 4 t, output pulse width (%) relative frequency of occurrence 2 1 0 1 2 15 14 13 12 11 10 9 8 7 6 5 v dd , supply voltage (volts) normalized pulse width change with respect to value at v dd = 10 v (%) t a = 25 c r x = 100 k c x = 0.1 f 0% point pulse width v dd = 5.0 v, t = 9.8 ms v dd = 10 v, t = 10 ms v dd = 15 v, t = 10.2 ms r x = 100 k c x = 0.1 f figure 7. typical total supply current versus output duty cycle total supply current ( a) m 1000 100 10 1.0 0.1 0.001 0.1 1.0 10 100 output duty cycle (%) r x = 100 k , c l = 50 pf one monostable switching only v dd = 15 v 10 v 5.0 v function table inputs outputs reset a b q q h h h l h l not triggered h h not triggered h l, h, h not triggered h l l, h, not triggered l x x l h x x not triggered
MC14538B http://onsemi.com 7 figure 8. typical error of pulse width equation versus temperature figure 9. typical error of pulse width equation versus temperature -2 -1 0 1 2 -60 -40 -20 0 20 40 60 80 100 120 140 t a , ambient temperature ( c) typical normalized error with respect to 25 dd = 10 v (% ) c value at v r x = 100 k c x = 0.1 f v dd = 15 v v dd = 10 v v dd = 5 v -2.0 -1.0 0 1.0 2.0 3.0 -3.0 -60 -40 -20 0 20 40 60 80 100 120 140 t a , ambient temperature ( c) r x = 100 k c x = .002 f v dd = 15 v v dd = 10 v v dd = 5.0 v typical normalized error with respect to 25 dd = 10 v (% ) c value at v theory of operation 2 figure 10. timing operation positive edge re?trigger (pulse lengthening) positive edge trigger 1 2 3 4 5 1 3 4 5 reset a b c x /r x q v ref1 v ref1 v ref1 v ref1 v ref2 v ref2 v ref2 v ref2 t t t negative edge trigger positive edge trigger positive edge re?trigger (pulse lengthening)
MC14538B http://onsemi.com 8 trigger operation the block diagram of the MC14538B is shown in figure 1, with circuit operation following. as shown in figure 1 and 10, before an input trigger occurs, the monostable is in the quiescent state with the q output low, and the timing capacitor c x completely charged to v dd . when the trigger input a goes from v ss to v dd (while inputs b and reset are held to v dd ) a valid trigger is recognized, which turns on comparator c1 and n?channel transistor n1 . at the same time the output latch is set. with transistor n1 on, the capacitor c x rapidly discharges toward v ss until v ref1 is reached. at this point the output of comparator c1 changes state and transistor n1 turns off. comparator c1 then turns off while at the same time comparator c2 turns on. w ith transistor n1 off, the capacitor c x begins to charge through the timing resistor, r x , toward v dd . when the voltage across c x equals v ref 2 , comparator c2 changes state, causing the output latch to reset (q goes low) while at the same time disabling comparator c2 . this ends at the timing cycle with the monostable in the quiescent state, waiting for the next trigger. in the quiescent state, c x is fully charged to v dd causing the current through resistor r x to be zero. both comparators are aoffo with total device current due only to reverse junction leakages. an added feature of the MC14538B is that the output latch is set via the input trigger without regard to the capacitor voltage. thus, propagation delay from trigger to q is independent of the value of c x , r x , or the duty cycle of the input waveform. retrigger operation the MC14538B is retriggered if a valid trigger occurs a followed by another valid trigger ? before the q output has returned to the quiescent (zero) state. any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from v ref 1 , but has not yet reached v ref 2 , will cause an increase in output pulse width t. when a valid retrigger is initiated ? , the voltage at c x /r x will again drop to v ref 1 before progressing along the rc charging curve toward v dd . the q output will remain high until time t, after the last valid retrigger. reset operation the MC14538B may be reset during the generation of the output pulse. in the reset mode of operation, an input pulse on reset sets the reset latch and causes the capacitor to be fast charged to v dd by turning on transistor p1 ? . when the voltage on the capacitor reaches v ref 2 , the reset latch will clear, and will then be ready to accept another pulse. it the reset input is held low, any trigger inputs that occur will be inhibited and the q and q outputs of the output latch will not change. since the q output is reset when an input low level is detected on the reset input, the output pulse t can be made significantly shorter than the minimum pulse width specification. power?down considerations large capacitance values can cause problems due to the large amount of energy stored. when a system containing the MC14538B is powered down, the capacitor voltage may discharge from v dd through the standard protection diodes at pin 2 or 14. current through the protection diodes should be limited to 10 ma and therefore the discharge time of the v dd supply must not be faster than (v dd ). (c) / (10 ma). for example, if v dd = 10 v and c x = 10 f, the v dd supply should discharge no faster than (10 v) x (10 f) / (10 ma) = 10 ms. this is normally not a problem since power supplies are heavily filtered and cannot discharge at this rate. when a more rapid decrease of v dd to zero volts occurs, the MC14538B can sustain damage. to avoid this possibility use an external clamping diode, d x , connected as shown in fig. 11. figure 11. use of a diode to limit power down current surge v ss d x v dd v dd r x c x q q reset
MC14538B http://onsemi.com 9 figure 12. retriggerable monostables circuitry figure 13. non?retriggerable monostables circuitry c x r x v dd q q reset = v dd b = v dd a b rising-edge trigger c x r x v dd q q reset = v dd b a = v ss falling-edge trigger c x r x v dd q q a b reset = v dd c x r x v dd q q reset = v dd a b falling-edge trigger rising-edge trigger nc nc nc v dd v dd a b figure 14. connection of unused sections q q c d typical applications
MC14538B http://onsemi.com 10 package dimensions pdip?16 p suffix plastic dip package case 648?08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic?16 d suffix plastic soic package case 751b?05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
MC14538B http://onsemi.com 11 package dimensions soic?16 wb dw suffix plastic soic package case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 tssop?16 dt suffix plastic tssop package case 948f?01 issue a ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 -u- s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n
MC14538B http://onsemi.com 12 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj?16 f suffix plastic eiaj soic package case 966?01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MC14538B/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

▲Up To Search▲

Price & Availability of MC14538B

	To Download MC14538B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .